The present invention relates to generation of clock signals for integrated circuits and, more particularly, to comparators and relaxation oscillators that use comparators.
Relaxation oscillator circuits are found in many electronic circuit applications and are often used for generating clock signals that control the timing of such electronic circuits. For example, relaxation oscillator circuits can be used DC/DC converters, counters, shifting modules, microcontrollers and modulation circuitry. Typically, the period of the clock signal provided by a relaxation oscillator circuit is determined primarily by charging and discharging of two capacitors. Such charging and discharging is often controlled by current sources or current mirrors supplying charge currents to the capacitors and the discharging is effected by controlling transistors coupled across the capacitors.
The charging and discharging of the capacitors typically provides ramp or saw-tooth waveform inputs to complementary comparators and the outputs of these comparators provides pulses that form an output waveform of the oscillator circuit. However, comparators have inherent low to high and high to low transition delays that can affect the upper limits and accuracy of the frequency of the oscillator circuit. Furthermore, such inherent transition delays are undesirable for comparator circuits that require a rapid response time.
Comparators are often designed to have rapid response times in order to reduce either or both of the low to high and high to low transition delays. However, such rapid response times are obtained at the expense of relatively large and undesirable quiescent currents that flow through either or both pull up and pull down transistors. It would therefore be beneficial to both relaxation oscillator circuits and comparators in general if the rapid response times are obtained without the use of relatively large quiescent currents.